VLSI PROJECTS

S.NoVLSI TITLES
1Hardware Design of an Energy-Efficient High-Throughput Median Filter
2Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter
3A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
4Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary signed Digit number system
5Basic-Set Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields
6A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops
7Design of Low Power 8-Bit Carry Select Adder Using Adiabatic Logic
8Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers.
9Fm0 and Manchester Encoding Using Sols Technique with Clock Gating & Power Gating Methods
10FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications
11A Low-Power Yet High-Speed Configurable Adder for Approximate Computing
12A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
13Chip Design for Turbo Encoder Module for In-Vehicle System
14Efficient Modular Adders based on Reversible Circuits
15Power Efficient  Approximate Multipliers in LMS Adaptive Filters
16MAES: Modified Advanced Encryption Standard for Resource Constraint Environments
17Binary To Gray Code Converter Implementation Using QCA
18A Low-Power High-Speed Comparator for Precise Applications
19A High Performance Gated Voltage Level Translator with Integrated Multiplexer
20Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
21Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
22High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop
23Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder
24Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis
25 Analysis of vedic multiplier using various adder topologies
26Reconfigurable delay optimized carry select adder
27Analysis and Design of Low-Power Reversible Carry Select Adder Using D-Latch
28Design of Area and Delay Efficient Vedic MultiplierUsing Carry Select Adder
29An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA
30Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
31Reconfigurable Constant Multiplication for FPGAs
32RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing.
33DESIGN OF POWER AND AREA EFFICIENT APPROXIMATE MULTIPLIERS.
34DESIGN OF EFFICIENT BCD ADDERS IN QUANTUM-DOT CELLULAR AUTOMATION.
35Implementation of Multiplier Architecture Using Efficient Carry Select adders for synthesizing FIR filters.
36ASIC Implementation of Distributed Arithmetic in Adaptive FIR Filter
37VLSI Implementation of Boolean Algebra based Cryptographic Algorithm
38Iterative Architecture AES for Secure VLSI based System Design
39Novel Structure for Area-Efficient Implementation of FIR Filters
40Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
41Graph-Based Transistor Network Generation Method for Supergate Design
42A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
43Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
44A Comparative Study of FIR Filters using Vedic and Booths Algorithm
45High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
46An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics
47A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard
48Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
49Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
50Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors.
51TOSAM:AnEnergy-EfficientTruncation-andRounding-BasedScalableApproximate Multiplier
52Efficient Modular Adder Designs Based on Thermometer & One-Hot Encoding
53FPGA Based Implementation of FIR Filter for FOFDM Waveform
54Design And Analysis Of Approximate Redundant Binary Multipliers.
55Design of Reversible Arithmetic Logic Unit with Built-in Testability
56A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapath.
57Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems
58Low power approximate unsigned multipliers with configurable error recovery
59A Two Speed Radix -4 Serial –Parallel Multiplier
60Performance Analysis of Wallace Tree Multiplier with Kogge Stone Adder using 15-4 Compressor
61Concurrent Error Detectable Carry Select Adder with Easy Testability
62Design and Analysis of Majority Logic Based
Approximate Adders and Multipliers
63Block-based Carry Speculative Approximate
Adder for Energy-Efficient Applications
64Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
65RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
66Design of Efficient BCD Adders in Quantum-Dot Cellular Automata
67Power Delay Product Optimized Hybrid Full Adder Circuits
68Analysis of Vedic Multiplier using Various Adder Topologies
69Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic Line Decoders
70Fm0 and Manchester Encoding Using Sols Technique with Clock Gating & Power Gating Methods
71Reconfigurable Delay Optimized Carry Select Adder
72 
73VLSI Design for Convolutive Blind Source Separation
74Reconfigurable Constant Multiplication for FPGAs
75Design of Power and Area Efficient Approximate Multipliers
76Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
77A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on
CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm
78Design of Low Power 8-Bit Carry Select Adder Using Adiabatic Logic
79Hardware Design of an Energy-Efficient High-Throughput Median Filter
80VLSI Implementation of 3D Integer DCT for Video Coding Standards
81Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
82Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
83Delay Efficient Error Detection and Correction of Parallel IIR Filters using VLSI Algorithms
84Addition of Miller and Inverted Manchester Encoding Technique to Dedicated Short Range Communication with Full Hardware Utilization
85Analysis and Design of Low-Power Reversible Carry Select Adder Using D-Latch
86A Modified Partial Product Generator for Redundant Binary Multipliers
87An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
88A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
89Design of Delay Efficient Modified 16 bit Wallace Multiplier
90LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER
91A Cellular Network Architecture With Polynomial Weight Functions
92Carry Speculative Adder with Variable Latency for Low Power VLSI
93A New VLSI Algorithm for a High-Throughput Implementation of Type IV DCT
94Design and Implementation of 64 Bit Multiplier using Vedic Algorithm
95VLSI Architecture for delay efficient 32-bit Multiplier using Vedic Mathematic sutras
96Delay Efficient Error Detection and Correction of Parallel IIR Filters using VLSI Algorithms
97A Modified Partial Product Generator for Redundant Binary Multipliers
98Concept, Design, and Implementation of Reconfigurable CORDIC
99Design of Fast FIR Filter Using Compressor and Carry Select Adder
100Design and Optimization of 16×16 Bit Multiplier Using Vedic Mathematics
101High Performance VLSI Architecture for 3-D
Discrete Wavelet Transform
102Carry Speculative Adder with Variable Latency for Low Power VLSI
103Design of High Speed Carry Select Adder Using Brent Kung Adder
104VLSI Implementation of Boolean Algebra based Cryptographic Algorithm
105Iterative Architecture AES for Secure VLSI based System Design
106An Efficient VLSI Architecture for Discrete Hadamard Transform
107An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
108Low Power Array Multiplier Using Modified Full Adder
109A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
110Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
111Implementation of Multiplier Architecture Using Efficient Carry Select adders for synthesizing FIR filters
112Low-Power Parallel Chien Search Architecture
Using a Two-Step Approach
113Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression
114Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
115High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range ofSupply Voltage Levels
116A Comparative Study of FIR Filters using Vedic and Booths Algorithm
117Hybrid LUT/Multiplexer FPGA Logic Architectures
118VLSI Architecture for delay efficient 32-bit Multiplier using Vedic Mathematic sutras
119Low-Power and Area-Efficient Shift Register Using Pulsed Latches
120Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures
121Fault Tolerant Parallel Filters Based on Error Correction Codes
122Low-Complexity Tree Architecture for Finding the First Two Minima
123Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder
124VLSI Computational Architectures for the Arithmetic Cosine Transform
125Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
126Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
127A novel fault detection and correction technique for memory applications
128An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
129Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
130A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
131Optimized Designs of Reversible Fault Tolerant BCD adder and Fault Tolerant Reversible Carry Skip BCD Adder
132A Modified Partial Product Generator for Redundant Binary Multipliers
133OcNoC: Efficient One-cycle Router Implementation for 3D Mesh Network-on-Chip
134FPGA Implementation of Efficient Vedic Multiplier
135An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
136Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
137Multifunction Residue Architectures for Cryptography
138FPGA Implementation of Efficient Vedic Multiplier
139design of column bypass multiplier using Verilog HDL
140The Design of High Speed UART
141Enhanced Area Effi cient Architecture for 128 bit Modified CSLA
142DESIGN OF CANDY VENDING MACHINE USING VERILOG HDL
143Design 0f High Speed Multiplier using Reversible logic: a Vedic Mathematical Approach
144A high speed binary number multiplication using dadda algorithm
145Low Power Wallace Tree Multiplier Using Modified Full Adder
146design and implementation of Traffic light controller using verilog HDL
147Design of High speed VedicMultiplier using urdhva trayagyam
148DESIGN OF SEQUENCE DETECTOR USING VERILOG HDL
149DESIGN OF 16 BIT BARREL SHIFTER USING VERILOG HDL
150Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
151Design of Convolutional   Encoder Using Verilog HDL
152RTL Design and VLSI Implementation of an efficient Convolutional Encoder
153DESIGN OF SIMPLE VENDING MACHINE USING VERILOG HDL
154Design of digital clock using Verilog HDL
155FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile WiMAX)
156Design of FIR Filter using Verilog HDL
157Design Of FSM based Sequence Detector
158Design and Implementation of DES
159design and implementation of automatic washing machine using verilog HDL
160Low Power ALU Design By Ancient Mathematics